1. Field of the Invention
The present invention relates to a power on reset (POR) circuit which is mounted on a semiconductor integrated circuit and generates a reset signal (a rising edge waveform or a falling edge waveform) when it detects a ramp-up or a ramp-down of the supply voltage at power-on of the semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a configuration of a conventional POR circuit. FIG. 2 shows simulated waveforms obtained from the POR circuit of FIG. 1 when the power is turned on, with the voltage rise time tON of 10 xcexcs, and at restoration from the deep power down (DPWD) mode. FIGS. 3A, 3B, and 3C show simulated waveforms obtained from the POR circuit of FIG. 1 when the power is turned on, with the voltage rise time tON of 50 xcexcs, 10 xcexcs, and 5 xcexcs, respectively.
As shown in FIG. 1, the POR circuit includes a signal generator 10 having a PMOS transistor 11, a resistor 12, and a resistor 13, and an edge generator 20 having a resistor 21, an NMOS transistor 22, and an inverter 23.
When the semiconductor integrated circuit containing the POR circuit of FIG. 1 is powered up (during a period of 0 to 10 xcexcs on the time axis shown in FIG. 2), the ground line GL carries a ground voltage VSS (0 V, for instance), and the supply voltage VDD of the power supply line PL changes from low (L) level (0 V, for instance) to high (H) level (5 V, for instance). In the meantime, the DPWD signal input to the DPWD input port 31 is at low level (0 V, for instance). As the supply voltage VDD rises, a voltage of a first signal S1 generated at a first node n1 increases from the ground voltage VSS, increasing a voltage of a second signal S2 generated at a second node n2. Then, when the NMOS transistor 22 turns on, the voltage of the second signal S2 at the second node n2 decreases, causing the inverter 23 to generate a rising edge waveform. The rising edge waveform (i.e., a reset signal) A0(10) or A0(50) is output as a POR output from the POR output port 32 at about a time point of 6 xcexcs on the time axis shown in FIG. 2 or FIG. 3B, or at about a time point of 29 xcexcs on the time axis shown in FIG. 3A. When receiving the reset signal (the edge waveform A0(10) or A0(50), for instance), the semiconductor integrated circuit returns its state to a prescribed initial state.
The DPWD mode belongs to a power-saving mode of the semiconductor integrated circuit. In the DPWD mode, since the DPWD signal applied to the DPWD input port 31 is at high level (5 V, for instance), a penetration current that would flow from the power supply line PL to the ground line GL is eliminated in the POR circuit. When the semiconductor integrated circuit is restored from the DPWD mode (during a period of 14 xcexcs to 26.5 xcexcs on the time axis shown in FIG. 2), the DPWD signal input to the POR circuit is switched from high level to low level. After that, the voltage of the first signal S1 at the first node n1 gradually increases. Then, when the NMOS transistor 22 turns on, the voltage of the second signal S2 at the second node n2 decreases, causing the inverter 23 to generate a rising edge waveform. The rising edge waveform (i.e., a reset signal) B0 is output as a POR output from the POR output port 32 at about a time point of 27.5 xcexcs on the time axis shown in FIG. 2.
As has been described above, the POR circuit shown in FIG. 1 outputs the reset signal even at restoration from the DPWD mode. However, because the DPWD mode belongs to a power-saving mode, after restoration from the DPWD mode, there are needs for continuing the processing that were being performed before the transition to the DPWD mode, that is, needs for inhibiting the output of the reset signal at restoration from the DPWD mode.
As shown in FIGS. 3A and 3B, the POR circuit shown in FIG. 1 can generate an edge waveform as a reset signal if the rise time tON of the supply voltage VDD at power-on long enough (50 xcexcs or 10 xcexcs, for instance). If the supply voltage VDD quickly rises, that is, if the rise time tON is short (5 xcexcs, for instance), as shown in FIG. 3C, an edge waveform as a reset signal cannot be generated.
It is an object of the present invention to provide a POR circuit which outputs a reset signal at power-on of the semiconductor integrated circuit and does not output a reset signal at restoration from the DPWD mode.
It is another object of the present invention to provide a POR circuit which can reliably output a reset signal even when the supply voltage quickly rises at power-on of the semiconductor integrated circuit.
According to the present invention, a POR circuit includes a power supply line; a first port to which a power-saving mode signal is input; a second port from which a reset signal is output; a signal generator which is controlled in accordance with the power-saving mode signal to generate a control signal; an edge generator which is controlled in accordance with the control signal to generate an edge signal; a first delay circuit which outputs a delayed power-saving mode signal obtained by delaying the power-saving mode signal; a charging circuit which is controlled in accordance with the delayed power-saving mode signal to speed up charging of a first node where the control signal is generated at restoration from the power-saving mode; and an output inhibit circuit which outputs an edge waveform as a reset signal from the second port during a period of changing from a power-off state, in which no power is supplied to the power supply line, to a power-on state, in which power is supplied to the power supply line, and does not output the reset signal from the second port when a voltage of the power-saving mode signal is changed.